The present disclosure relates to a semiconductor structure, and particularly to a semiconductor structure including a deep isolation trench and a deep capacitor trench on a semiconductor-on-insulator substrate and a method of manufacturing the same.
Deep trench capacitors are used in a variety of semiconductor chips for high areal capacitance and low device leakage. Typically, a deep trench capacitor provides a capacitance in the range from 4 fF (femto-Farad) to 120 fF. A deep trench capacitor may be employed as a charge storage unit in a dynamic random access memory (DRAM), which may be provided as a stand-alone semiconductor chip, or may be embedded in a system-on-chip (SoC) semiconductor chip. A deep trench capacitor may also be employed in a variety of circuit applications such as a charge pump or a capacitive analog component in a radio-frequency (RF) circuit.
Integration of deep trench capacitors on a semiconductor-on-insulator (SOI) substrate to form embedded DRAM (eDRAM) devices requires electrical isolation between logic device areas and eDRAM areas. Deep isolation trench structures provide superior electrical isolation between adjacent device regions compared to shallow isolation trench structures. However, formation of deep isolation trench structures typically requires extra processing steps because deep isolation trench structures require a thicker dielectric material than a node dielectric of deep trench capacitors. Adding processing steps in the art for formation of deep isolation trench structures to a conventional process flow for forming a DRAM device significantly increases the total processing time and production cost for embedded SOI devices employing deep isolation trench structures.